Please refer to FIG. 1 that is a functional block diagram showing a computer system operated with Peripheral Component Interconnect (PCI) Express Protocol. In FIG. 1, CPU 10, north bridge chip 11, south bridge chip 12, power 13 and PCI Express devices 140, 141, 142, 143 and 144 are illustrated. The north bridge chip 11 serves as a root complex of the whole PCI Express system, and there is Express Link existing between each PCI Express device and the root complex.
For implementing power management of the above computer system, the computer operating system utilizes a write cycle to write data into a power management I/O port in the south bridge chip 12, thereby entering one of different power-saving states S1, S3, S4 and S5. The state S1 indicates a standby mode. The state S3 indicates a STR mode, which is usually entered to shut down the power supplied to the CPU 10 and other devices such as a hard disc drive after the computer system has stored specific data to the random access memory (RAM). Nevertheless, the power supplied to a RAM is reserved to prevent from data loss and quickly restore the system by re-loading the specific data from the RAM. The state S4 indicates a STD mode wherein the computer system has stored specific data to a non-volatile memory such as a disk partition. The state S5 indicates a software-shutoff mode. In response to the write cycle, a power management unit 120 in the south bridge chip 12 asserts a clock-suspending signal STPCLK to the CPU 10. In response to the clock-suspending signal STPCLK, the CPU 10 is ready to enter a power-saving mode. Meanwhile, the CPU 10 asserts a clock-suspending grant cycle STPGNT to the south bridge chip 12 via the north bridge chip 11. In response to the clock-suspending grant cycle STPGNT, a SUSB signal indicative of the S3 state or a combination of SUSB and SUSC signals indicative of the S4 or S5 mode will be issued by the south bridge chip 12 to result in different kinds of power management. The system including the CPU 10 then enters the power-saving mode.
As mentioned above, in the PCI Express Protocol, there are a plurality of PCI Express devices connected to the north bridge chip 11. When the CPU 10 asserts a clock-suspending grant cycle STPGNT to the south bridge chip 12, the south bridge chip 12 will issue a SUSB signal or a combination of SUSB and SUSC signals to have the system enter the power-saving mode S3, S4 or S5. Accordingly, the power supplied to the PCI Express devices will be removed. Since such removal of power is unpredictable for both the PCI Express devices and the root complex, it may result in failure in subsequent re-initialization of these devices.